1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a dynamic random access memory (DRAM) with simplified refresh control.
2. Description of the Background Art
System LSIs such as a logic-embedded DRAM having the logic of a processor, an ASIC (Application Specific IC) or the like and a dynamic random access memory (DRAM) of a large capacity integrated on the same semiconductor chip (semiconductor substrate) have now been used this few years.
By the interconnection between the logic and the DRAM through a multibit internal data bus of 128 to 512 bits in a system LSI, data transfer at least one or two order of magnitude faster than the case where a general DRAM with few terminals and a logic LSI are connected and used on a printed circuit board can be realized
Also, the number of external pin terminals of the logic can be reduced than those of the system in which a general DRAM is externally provided with respect to the logic.
In a system LSI, the DRAM block and the logic are connected by internal wiling. Since the length of the internal wiring is sufficiently shorter than that on the print substrate so that parasitic capacitance is small, the discharge/charge current of the data bus can be reduced significantly and the signal can be transferred speedily.
By virtue of such factors, the DRAM-embedded system. LSI greatly contributes to improving the performance of information equipment that carries out a process handling a great amount of data such as the three-dimensional graphic processing, image and video processing, or the like.
FIG. 34 schematically shows a structure of a DRAM circuit block incorporated in a conventional system LSI.
Referring to FIG. 34, the DRAM circuit block includes plurality of memory arrays MA0-MAn, sense amplifier bands SB1-SBn arranged between memory arrays MA0-MAn, and sense amplifier bands SB0 and SBn+1 arranged outside memory arrays MA0 and MAn. Each of memory arrays MA0-MAn is divided into a plurality of memory subarrays MSA by a subword driver band SWDB.
In each of memory arrays MA0-MAn, a main word line MWL is arranged common to divided memory subarrays MSA divided by subword driver band SWDB. Main word line MWL is arranged corresponding to a predetermined number of subword lines, respectively, of each memory subarray MSA of the corresponding memory array. Main word line MWL and a predetermined number of subdecode lines SDL arranged on the sense amplifier band are connected to a subword driver in subword driver band SWDB to select one subword line.
Each of sense amplifier bands SB1-SBn is shared by adjacent memory arrays. Corresponding to memory arrays MA0-MAn are provided a row decoder to select a main word line and a subdecode line according to a row address signal, and a column decoder in alignment with the row decoder to transmit on a column select line CSL a column select signal to select a column from a memory array according to a column address signal.
Column select line CSL is arranged at the sense amplifier band to connect a predetermined number of sense amplifier circuits to a group of internal data line pairs GIOP when selected. A predetermined number of internal data line pairs GIOP are arranged extending over memory arrays MA0-MAn to be coupled to a sense amplifier circuit selected via a local data line.
Internal data line pair GIOP is coupled to a data path band DPB provided in 128 bits to 512 bits, including a preamplifier and a write driver. In this data path band DPB, a preamplifier and a write driver are arranged corresponding to respective internal data line pairs GIOP. Internal data line pair GIOP may be a transmission line pair that transmits both write and read data, or provided as an internal data line pair in which a bus line pair transmitting read data and a write data line pair transmitting write data are provided individually.
The DRAM circuit block further includes a row address input circuit/refresh counter RAFK and a column address input circuit CAK receiving, for example, 13-bit external addresses A0-A12 from the logic, a command decoder/control circuit CDC receiving external control signals CLK, CKE, /CS, /RAS, /CAS, /WE and DM applied from the logic, and a data input/output control circuit DIOK to transfer data between data path band DPB and the logic.
Command decoder/control circuit CDC receives a clock signal CLK, a clock enable signal CKE, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM to determine the specified operation mode according to the logic status at the rising edge of these control signals. In this case, “command” is specified by the combination of the logic states at the rising edge of a clock signal CLK of these plurality of control signals CKE, /RAS, /CAS and /WE.
Data mask signal DM designates a write mask in byte-by-byte with respect to the data applied to data input/output control circuit DIOK. Command decoder/control circuit CDC decodes the command applied from the logic. An operation mode designation signal designating the operation mode specified by this command is generated, whereby various internal control signals to carry out the specified operation mode is generated.
The command includes a row active command to set the row to a selected state, a read command designating data reading, a write command designating data writing, a precharge command to return the selected row to a non-selected state, an auto refresh command to carry out a refresh operation, a self refresh command to carry out self refresh, and the like.
Row address input circuit/refresh counter RAFK responds to application of a row active command to receive external address bits A0-A12 as the row address to generate an internal row address signal under control of command decoder/control circuit CDC.
Row address input circuit/refresh counter RAFK includes an address buffer to apply a buffer process on an applied address bit, and an address latch latching the output signal of the buffer circuit.
The refresh counter included in row address input circuit/refresh counter RAFK generates a refresh address designating the row to be refreshed when an auto refresh command or a self refresh command is applied. When the refresh operation is completed, the count value of this refresh counter is incremented or decremented.
Column address input circuit CAK responds to the application of a read command or write command to receive the bits of lower significance of the external address bits such as address bits A0-A4 to generate an internal column address signal under control of command decoder/control circuit CDC. This column address input circuit CAK includes an address buffer and an address latch.
The internal row address signal from row address input circuit/refresh counter RAFK is applied to a row predecoder RPD. The internal column address signal from column address input circuit CAK is applied to column predecoder CPD.
Row predecoder RPD predecodes the applied internal row address signal to provide the predecoded signal to the row decoder in row/column decoder band RCDB. Column predecoder CPD predecodes the internal column address signal from column address input circuit CAK to provide the predecoded signal to the column decoder in row/column decoder band RCDB.
Upon receiving a read command or a write command, command decoder/control circuit CDC generates an internal control signal to control the operation of the preamplifier and the write driver in data input/output control circuit DIOK and data path band DPB. Clock signal CLK is used as a reference signal determining the internal operation timing of the DRAM circuit block.
Data input/output control circuit DIOK inputs/outputs data in synchronization with clock signal CLK. The row address input circuit of row address input circuit/refresh counter RAFK and column address input circuit CAK receive and latch the applied address bit in synchronization with clock signal CLK.
The DRAM circuit block further includes a block PHK which has an internal voltage generation circuit generating internal voltages VPP, VCCS, VCCP, VBL and a self refresh timer rendering a refresh request signal FAY active at a predetermined interval when a self refresh mode is specified, i.e. when command COM applied from command decoder/control circuit CDC is a self refresh command.
Internal voltage VPP is transmitted on a selected subword line SWL, and has a voltage level generally higher than the operating power supply voltage. Voltage VCCS is the operating power supply voltage of the sense amplifier circuit in sense amplifier bands SB0˜SBn+1, generated by an internal voltage-down converter circuit not shown. Voltage VCCP is a periphery power supply voltage generated by an internal voltage-down converter circuit not shown, and the operating power supply voltage applied to the peripheral circuits such as the row decoder and column decoder in row/column decoder group RCDB and the preamplifier and write driver included in data path band DPB. Voltage VBL is a bit line precharge voltage. Voltage VCP is a cell plate voltage applied to the cell plate of a memory cell, taking a middle voltage between the H level voltage and the L level voltage of the memory cell data. Voltages VBL and VCP are middle voltages corresponding to ½ the array power supply voltage (sense power supply voltage).
The self refresh timer in the block PHK is rendered active upon entering a self refresh mode, and issues a refresh request signal FAY at a predetermined interval so that the refresh operations of all the rows in memory arrays MA0-MAn is completed once at the maximum refresh time tREFmax.
This self refresh mode is set generally when in a sleep mode, i.e. when the system LSI is at a standby state for over a long period of time. The charge stored in the capacitor in the memory cell is lost by various leakage current, for example, junction leakage current at a storage node SN, the channel leakage current of the memory cell transistor, the leakage current of the capacitor insulation film, or the like. Particularly in the case of writing H (high) data, refresh must be carried out before the difference between the voltage of a bit line which is read out from a memory cell and voltage VBL becomes lower than the sensitivity of the sense amplifier. Therefore, the data retain time of the entire chip is defined as tREFmax described in the foregoing depending upon the memory cell that has the shortest data retaining time in the chip.
Assuming that the number of refreshes required to refresh all the rows in memory arrays MA0-MAn is Nref, refresh request signal FAY is issued at the cycle of tREFmax/Nref. For example, in the 4K refresh mode of Nref=4096, refresh request signal FAY is issued for every 16 μs when the maximum refresh time tREFmax is 64 ms.
The system configuration of using an asynchronous general static random access memory (SRAM) that does not require supply of an external clock is widely employed in portable information terminals and the like. Since the memory that is required in high speed data processing is served by the cache memory incorporated in the processor, the function of high speed access is not required in an externally-provided data retaining SRAM.
Therefore, in order to simplify the system configuration in portable information terminals and the like that have severe requirement for reduction in size, a general purpose SRAM is employed that does not require complicated memory control associated with the refresh operation every each refresh cycle or control of suspending access to the currently-refreshed memory until the refresh cycle ends.
However, portable information terminals are significantly improved in the feature of handling images these few years, requiring the memory function of a large capacity. For SRAMs that have a memory size approximately ten times larger than that of the memory cells of DRAMs, the cost of the chip will be increased significantly by the memory of large capacity which results in raising the cost of the portable information terminal. Expectations are high for a DRAM as a substitute for SRAM.
Particularly for the embedded DRAM having a DRAM of large capacity integrated with the logic of high complexity or a microprocessor, high speed data transfer is allowed even if the operating frequency is set low by using an internal data bus of multibits. Furthermore, power consumption during operation can be reduced. Therefore, expectations towards application of a system LSI such as a logic-embedded DRAM is high. However, usage of a DRAM as a substitute for the SRAM is not so simple since the DRAM requires complicated memory control as to refresh.